Non-volatile logic (NVL) is a ferro-magnetic random access memory (FRAM) based state retention technology that combines characteristics of FRAM memory with current data retention methods. Generally speaking, FRAM's comprise a non-volatile memory technology that typically operate by changing the polarity of a capacitor dielectric to switch between two stable states having corresponding different capacitive values. These two stable states correspond to stored “1's” and “0's.”
More specifically, the fundamental storage element of FRAM is a ferroelectric capacitor. FIG. 1 illustrates a ferroelectric capacitor 105 used in a 1T-1C (one transistor—one capacitor) FRAM memory cell. The capacitor 105 can be polarized “up” or “down” by applying a positive or negative electrical field to it. The voltage for this operation is provided by a standard MOSFET circuit in a WL/BL/PL (word line/bit line/plate line) based memory circuit with a transistor 110. Consequently, the FRAM behaves similar to DRAM (dynamic random access memory) with regard to changing the charge of the capacitor. The primary difference is that a ferroelectric capacitor retains its state permanently.
Major characteristics of FRAM include: 1) FRAM is nonvolatile, implying that the data information is retained when no power is attached to the FRAM cell; 2) FRAM has similar read/write times compared to SRAM (static random access memory) and provides random access without memory segmentation; 3) the write energy is extremely low because FRAM can be accessed by a default power domain, VDD, in a system on a chip (SoC) architecture and does not require a charge pump like flash memory; and 4) FRAM provides higher endurance compared to floating gate memories because FRAM accesses do not degrade to the storage cell.
Thus, FRAM combines the advantages of RAM and nonvolatile memories, particularly with respect to having short read/write times, which are similar to SRAM, and low power consumption. Moreover, FRAM provides practically unlimited endurance because the read/write cycles of a single cell are in the order of 1015 cycles.
The ferroelectric capacitor consists of a film of crystalline structure between the two electrode plates. FIG. 2 illustrates the crystal in detail. The ferroelectric dipole is formed by a zirconium/titanium (Zr/Ti) atom and oxygen (O) atoms within the lead (Pb) crystal. The material is therefore called lead-zirkonate-titanate (PZT).
By applying an appropriate electrical field across the crystal, the mobile Ti atom moves from one stable state (“Up Polarization”) to another stable state (“Down Polarization”) within the crystal lattice. With increasing field strength the mobile atom crosses the barrier formed by the O atoms and flips to the second stable state, thus changing the polarization state of the unit cell. Because the state of the mobile Ti atom is retained after the power is removed, the ferroelectric dipole is non-volatile. The behavior of the PZT material results in a hysteresis loop, which can be compared to the magnetic BH curve.
In a read process, the current charge of the ferroelectric capacitor is sensed by using the ferroelectric capacitor as one capacitor in a capacitor divider. Depending on the stored data, one of two different voltages are gained on the bitline placed as the middle node of the capacitive divider, which voltages are then developed by a sense amplifier. Because this procedure has impact on the current state of the dipole, the read value has to be restored into the capacitor again. This step usually takes place directly in the same read sequence. The write and read control sequences are already known from current DRAM operations.